The Interconnect Nobody Can Buy

The UALink Consortium ratified its 2.0 specification on 7 April 2026, adding in-network compute, chiplet definitions, and manageability to an interconnect standard designed to link up to 1,024 accelerators within an AI computing pod. The press release went to the usual outlets. The technical brief promised 200Gbps throughput per lane and an open ecosystem free from single-vendor lock. AMD, Intel, Meta, Hewlett-Packard Enterprise, Amazon Web Services, Apple, Cisco, Google, Lightmatter, Microsoft, and Synopsys are all listed as consortium members. It reads like the coalition you would want if you were trying to break NVIDIA's grip on scale-up interconnect.

Despite the group's initial standard dropping last spring, little to no 1.0-compliant hardware is available at the time of writing, with most systems still in the production phase. That sentence, buried in an SDxCentral article from April, is the one that matters if you are sitting in procurement trying to spec a cluster for delivery in Q1 2027. UALink 2.0 is a document. It is not silicon you can install, and it is not a switch ASIC you can order on a datasheet with a delivery window. As of 2026, limited shipping hardware uses UALink, with broader silicon availability expected in 2026-2027. Expected. The verb is doing most of the work.

The alternative you can contract for today is NVIDIA's stack: NVLink features up to 1.8 TB/s of bi-directional bandwidth per GPU, supporting up to 72 GPUs per rack, and the larger pods run over NVIDIA Quantum-2 400 Gb/s InfiniBand between nodes. That gives you approximately 350 GB/s effective all-reduce bandwidth with NCCL on an eight-node H100 cluster using InfiniBand NDR 400G. The performance is known. The interoperability between NVLink, NVSwitch, and InfiniBand is shipped and debugged. The software stack is production-hardened across every major hyperscaler and most serious AI labs. You know the price, you know the lead time (which is bad, but it is a known bad), and you know what utilisation to model.

If you sign off on a UALink-based architecture today, you are betting on a roadmap, not a part number. The question is not whether the standard is technically credible. It is. The working groups include serious engineers from serious companies, and the bandwidth and latency targets are grounded in what 2026 silicon can do. The question is whether production-ready silicon, validated switch ASICs, interoperable NICs, stable drivers, and a communication library that works at scale will all arrive in time to meet the commissioning date you just committed to in front of the board. And if any one of those pieces slips by three months, what is your fallback, and does it cost you penalty clauses or another quarter of revenue you cannot bill?

RDMA over Converged Ethernet offers a third path. RoCE (RDMA over Converged Ethernet) runs the InfiniBand RDMA transport layer over an Ethernet-based packet-switched network, with Version 2 encapsulating InfiniBand packets in UDP datagrams, which means you can build the cluster on commodity Ethernet infrastructure and still get GPU-direct memory access without CPU overhead. Standard 400GbE RoCEv2 delivers 270-290 GB/s effective under the same conditions where InfiniBand NDR hits 350 GB/s. That is a 20% haircut on all-reduce bandwidth, which translates directly into longer training times and lower cluster utilisation. GPU clusters for AI training operate at only 30-50% efficiency due to poor inter-GPU communication, availability issues, and tail latency from slow straggler GPUs. You start at 30-50%, then you take another 20% hit on fabric throughput. The arithmetic is unforgiving.

The other problem with RoCE is that it was designed to coexist with other traffic, but a decade later, several of its shortcomings must be addressed to fulfill the demands of hyperscale datacenters, according to a peer-reviewed paper published by researchers from ETH Zurich, Microsoft, HPE, and Broadcom. RoCE relies on Priority Flow Control to ensure a lossless network, but PFC brings certain side effects, such as Head-of-Line blocking, congestion spreading, and deadlock. Those are not edge cases. They are the failure modes that show up when you scale past a few hundred GPUs and the fabric starts to behave like a distributed system with emergent pathologies nobody modelled in the pilot. You can tune PFC, add ECN-based congestion control, segment the network into failure domains, and run it in production. Plenty of people do. But you are managing complexity that InfiniBand does not have, and complexity has a recurring operational cost that never appears on the CapEx comparison slide.

The other cost that does not appear on the slide is HBM. As of August 2026, HBM3 costs approximately $200 per 24GB stack, HBM3E costs ~$300 per 36GB stack, and next-generation HBM4 is expected at ~$550 per 36GB stack. HBM now represents 30-40% of total AI accelerator manufacturing cost, up from under 20% two generations ago. That is before packaging. CoWoS-S packaging costs approximately $750 per chip for H100-class designs; CoWoS-L costs $1,000-$1,100 for NVIDIA's B200, a 47% premium driven by multi-die complexity. Memory and packaging together are now the dominant cost in an AI accelerator, which means the logic die you are waiting for is no longer the long pole. The long pole is TSMC's monthly CoWoS capacity, which could reach 120,000 to 140,000 wafers in 2026, and NVIDIA is consuming approximately 60% of that allocation.

If you are buying NVIDIA, you are in a queue, and the queue is long. If you are buying AMD MI325X or MI455X with AMD pivoting from Infinity Fabric to the open UALink standard, with MI400 rack-scale solutions expected H2 2026, you are in a different queue for HBM4, and that queue does not clear until Samsung, SK Hynix and Micron ramp production in late 2025 to 2026, with the NVIDIA Rubin and AMD MI455X platforms pulling HBM4 into volume. Supply remains constrained through 2026, with lead times for HBM3E stacks at 20-26 weeks. The interconnect is one variable. The memory is another. The packaging is a third. Any one of them can gate the whole purchase order.

The case for waiting on UALink is that the standard is real, the roadmap is funded, and every hyperscaler not named NVIDIA has an incentive to see it succeed. The case against is that incentives are not shipping dates. Additional UALink silicon is expected from AMD's partners in 2026-2027. Expected, again. The verb you actually need is "available for order with a confirmed delivery window and a penalty clause if it slips." That verb does not appear in any press release I have seen.

I would not sign a contract today that depends on UALink hardware being available in Q1 2027 unless the vendor is willing to put a financially binding delivery commitment in the contract, not a roadmap slide. If they will not, then the cluster you are buying is NVIDIA NVLink over InfiniBand, or it is AMD with Infinity Fabric on whatever AMD can actually ship by the contract date, or it is RoCE on Ethernet with the performance and operational overhead that come with it. The standard you want and the silicon you can install are not the same thing, and the gap between them is measured in quarters you cannot get back.

Tarry Singh is the founder and CEO of Real AI (realai.eu), an enterprise AI advisory and deployment firm working with global enterprises on production agent systems, model risk, and AI sovereignty strategy. He also leads Earthscan (earthscan.io) for Energy AI, and is a founding contributor to the EU-funded HCAIM and PANORAIMA programmes for responsible AI education across European universities. He writes at tarrysingh.com.